Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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Recently defined, three-level logic sum of pseudo-products (SPP) forms are EXOR-AND-OR networks representing Boolean functions, and are much shorter than standard two-level sum of products (SOP) expressions (Luccio and Pagli, 1999). The main disadvantages of SPP networks are their cumbersome theory in the original formulation and their high minimization time. In addition, the current technology cannot efficiently implement the unbounded fanin EXOR gates of SPP expressions. In this paper, we rephrase SPP theory in an algebraic context to obtain an easier description of the networks. We define a new model of SPP networks (k-SPP) with bounded fanin EXOR gates, whose minimization time is strongly reduced and whose minimal forms are still very compact. In the Boolean space {0,1}n, a k-SPP form contains EXOR gates with at most k literals, where 1 ≤ k ≤ n. The limit case k = n corresponds to SPP networks and k = 1 to SOPs. Finally, we perform an extensive set of experiments on classical benchmarks. In order to validate our approach, the results are compared with those obtained for the major two- and three-level forms using standard metrics.