Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
On a New Boolean Function with Applications
IEEE Transactions on Computers
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Synthesis of SPP three-level logic networks using affine spaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
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The paper presents a heuristic algorithm for the minimization of 2-SPP networks, i.e., three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. Previous works had presented exact algorithms for the minimization of unrestricted SPP networks and of 2-SPP networks. The exact minimization procedures were formulated as covering problems as in the minimization of SOP forms and had worst-case exponential complexity. Extending the expand-irredundant-reduce paradigm of the ESPRESSO heuristic, we propose a minimization algorithm for 2-SPP networks that iterates local minimization and reshape of a solution until further improvement. We introduce also the notion of EXOR-irredundant to prove that OR-AND-EXOR irredundant networks are fully testable and guarantee that our algorithm yields OR-AND-EXOR irredundant solutions. We report a large set of experiments showing impressive high-quality results with affordable run times, handling also examples whose exact solutions could not be computed.