Synthesis by spectral translation using Boolean decision diagrams
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Novel CNTFET-based reconfigurable logic gate design
Proceedings of the 44th annual Design Automation Conference
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Universal Logic Modules and Their Applications
IEEE Transactions on Computers
Programmable logic circuits based on ambipolar CNFET
Proceedings of the 45th annual Design Automation Conference
The universal logic block (ULB) and its application to logic design
SWAT '66 Proceedings of the 7th Annual Symposium on Switching and Automata Theory (swat 1966)
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Towards structured ASICs using polarity-tunable Si nanowire transistors
Proceedings of the 50th Annual Design Automation Conference
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Double-gate carbon nanotube field-effect transistors (DG-CNT-FETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.