Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors
Proceedings of the 49th Annual Design Automation Conference
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MIS: A Multiple-Level Logic Optimization System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards structured ASICs using polarity-tunable Si nanowire transistors
Proceedings of the 50th Annual Design Automation Conference
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Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics simultaneously. In this paper, we show that, by engineering of the contacts and by constructing independent double-gate structures, the device polarity can be electrostatically programmed to be either n- or p-type. Such a device enables a compact realization of XOR-based logic functions at the cost of a denser interconnect. To mitigate the added area/routing overhead caused by the additional gate, an approach for designing an efficient regular layout, called Sea-of-Tiles is presented. Then, specific logic synthesis techniques, supporting the higher expressive power provided by this technology, are introduced and used to showcase the performance of the controllable-polarity NWFETs circuits in comparison with traditional CMOS circuits.