An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Inverter minimization in multi-level logic networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Maximum projections of don't care conditions in a Boolean network
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
A safe, efficient update protocol for openflow networks
Proceedings of the first workshop on Hot topics in software defined networks
Proceedings of the Conference on Design, Automation and Test in Europe
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
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MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.