Combinational logic optimization techniques in sequential logic synthesis
Combinational logic optimization techniques in sequential logic synthesis
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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Synthesis of finite state machines: logic optimization
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
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Design and implementation verification of finite state systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combining retiming and sequential redundancy addition and removal for sequential logic optimization
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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This paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RAR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove that the sequential redundancy addition and removal technique provides more possibilities for logic optimization.