Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Programmable logic circuits based on ambipolar CNFET
Proceedings of the 45th annual Design Automation Conference
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
A fast transistor-chaining algorithm for CMOS cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Towards structured ASICs using polarity-tunable Si nanowire transistors
Proceedings of the 50th Annual Design Automation Conference
Hi-index | 0.00 |
We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs). First, we address gate-level routing congestion by proposing compact layout techniques and novel symbolic-layout styles. Second, we design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks on the SoT. Our study shows that SoT with TileG2 and TileG1h2, on an average, outperforms the one with TileG1 and TileG3 by 16% and 10% in area utilization, respectively.