Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Three parameters to find functional decompositions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Multiple-valued logic synthesis and optimization
Logic Synthesis and Verification
Linear Models of Circuits Based on the Multivalued Components
Automation and Remote Control
Complexity of many-valued logics
Beyond two
Fibonacci Arithmetic Expressions
Automation and Remote Control
A fast method to derive minimum SOPs for decomposable functions
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Minimization of memory size for heterogeneous MDDs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
Novel synthesis and optimization of multi-level mixed polarity Reed-Muller functions
Journal of Computer Science and Technology
An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exact ESCT minimization for functions of up to six input variables
Integration, the VLSI Journal
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
2 variable Reed Muller binary decision diagrams
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
2 variable Reed Muller binary decision diagrams
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Functionally linear decomposition and synthesis of logic circuits for FPGAs
Proceedings of the 45th annual Design Automation Conference
Constructing a User Preference Ontology for Anti-spam Mail Systems
CAI '07 Proceedings of the 20th conference of the Canadian Society for Computational Studies of Intelligence on Advances in Artificial Intelligence
Design Methods of Radix Converters Using Arithmetic Decompositions
IEICE - Transactions on Information and Systems
Minimizing AND-EXOR Expressions for Multiple-Valued Two-Input Logic Functions
TAMC '09 Proceedings of the 6th Annual Conference on Theory and Applications of Models of Computation
Secure multiparty computations using a dial lock
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
Power consumption of logic circuits in ambipolar carbon nanotube technology
Proceedings of the Conference on Design, Automation and Test in Europe
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A set theory based method to derive network reliability expressions of complex system topologies
ACC'10 Proceedings of the 2010 international conference on Applied computing conference
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Pulsed para-neural networks (PPNN) based on MEXORs and counters
ISNN'05 Proceedings of the Second international conference on Advances in Neural Networks - Volume Part I
Secure computations in a minimal model using multiple-valued ESOP expressions
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Exact ESOP expressions for incompletely specified functions
Integration, the VLSI Journal
Compact DSOP and Partial DSOP Forms
Theory of Computing Systems
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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From the Publisher:Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.