Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
Logic Design and Switching Theory
Logic Design and Switching Theory
Representations of Discrete Functions
Representations of Discrete Functions
Compact Representations of Logic Functions using Heterogeneous MDDs
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Using lower bounds during dynamic BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose exact and heuristic algorithms for minimizing the memory size for heterogeneous Multivalued Decision Diagrams (MDDs). In a heterogeneous MDD, each multi-valued variable can take a different domain. To represent a binary logic function using a heterogeneous MDD, we partition the binary variables into groups, and treat the groups as multi-valued variables. Therefore, the memory size of a heterogeneous MDD depends on the partition of the binary variables. Our experimental results show that heterogeneous MDDs require smaller memory size than Reduced Ordered Binary Decision Diagrams (ROBDDs) and Free BDDs (FBDDs).