Dominator-based partitioning for delay optimization
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Delay driven AIG restructuring using slack budget management
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
Proceedings of the 45th annual Design Automation Conference
Timing-driven N-way decomposition
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
Decomposition of systems of Boolean functions determined by binary decision diagrams
Journal of Computer and Systems Sciences International
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expressions with smaller depths than the ones obtained by state-of-the-art techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.