Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
An algorithm for bi-decomposition of logic functions
Proceedings of the 38th annual Design Automation Conference
Structure of Computers and Computations
Structure of Computers and Computations
Logic synthesis for vlsi design
Logic synthesis for vlsi design
A new decomposition method for multilevel circuit design
EURO-DAC '91 Proceedings of the conference on European design automation
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Recursive Paradigm to Solve Boolean Relations
IEEE Transactions on Computers
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techniques to reduce the depth of the netlist due to the affordable computational cost. We present a novel n-way decomposition technique that improves bi-decomposition. The problem of decomposition is formulated as a Boolean relation which captures a larger set of possible solutions compared to bi-decomposition. The solution obtained from the Boolean relation improves the delay with near-zero cost in area. As it is shown on the experimental results, a considerable improvement is achieved on large netlists and even larger depending on which technology mapper is used.