Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications
ISMVL '99 Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic
A new decomposition method for multilevel circuit design
EURO-DAC '91 Proceedings of the conference on European design automation
Multi-level logic optimization
Logic Synthesis and Verification
Simplifying Boolean constraint solving for random simulation-vector generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
Artificial Intelligence Review
Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining
Artificial Intelligence Review
A BDD-based fast heuristic algorithm for disjoint decomposition
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
BDD-based two variable sharing extraction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bi-decomposition of function sets in multiple-valued logic for circuit design and data mining
Artificial intelligence in logic design
Artificial intelligence in logic design
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
Proceedings of the 45th annual Design Automation Conference
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Timing-driven N-way decomposition
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Cybernetics and Systems Analysis
Iterative layering: optimizing arithmetic circuits by structuring the information flow
Proceedings of the 2009 International Conference on Computer-Aided Design
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Bi-decomposition of large Boolean functions using blocking edge graphs
Proceedings of the International Conference on Computer-Aided Design
Improvements of the construction of exact minimal covers of boolean functions
EUROCAST'11 Proceedings of the 13th international conference on Computer Aided Systems Theory - Volume Part II
New & improved models for SAT-based bi-decomposition
Proceedings of the great lakes symposium on VLSI
Towards efficient MUS extraction
AI Communications - 18th RCRA International Workshop on “Experimental evaluation of algorithms for solving problems with combinatorial explosion”
Proceedings of the International Conference on Computer-Aided Design
QBF-based boolean function Bi-decomposition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don't-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably non-redundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.