An algorithm for bi-decomposition of logic functions
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
An Experimental Comparison of Min-Cut/Max-Flow Algorithms for Energy Minimization in Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
New & improved models for SAT-based bi-decomposition
Proceedings of the great lakes symposium on VLSI
QBF-based boolean function Bi-decomposition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Bi-decomposition techniques have been known to significantly reduce area, delay, and power during logic synthesis since they can explore multi-level and, or, and xor decompositions in a scalable technology-independent manner. The complexity of bi-decomposition techniques is in achieving a good variable partition for the given logic function. State-of-the-art techniques use heuristics and/or brute-force enumeration for variable partitioning, which results in sub-optimal results and/or poor scalability with function complexity. This paper describes a fast, scalable algorithm for obtaining provably optimum variable partitions for bi-decomposition of Boolean functions by constructing an undirected graph called the blocking edge graph (BEG). To the best of our knowledge, this is the first algorithm that demonstrates a systematic approach to derive disjoint and overlapping variable partitions for bi-decomposition. Since a BEG has only one vertex per input, our technique scales to Boolean functions with hundreds of inputs. Results indicate that on average, BEG-based bi-decomposition reduces the number of logic levels (mapped delay) of 16 benchmark circuits by 60%, 34%, 45%, and 30% (20%, 19%, 16% and 20%) over the best results of state-of-the-art tools FBDD, SIS, ABC, and an industry-standard synthesizer, respectively.