Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Restructuring logic representations with easily detectable simple disjunctive decompositions
Proceedings of the conference on Design, automation and test in Europe
Three parameters to find functional decompositions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An algorithm for bi-decomposition of logic functions
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification
Logic Synthesis and Verification
Quasi-algebraic decompositions of switching functions
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
BDD Decomposition for Efficient Logic Synthesis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Finding composition trees for multiple-valued functions
ISMVL '97 Proceedings of the 27th International Symposium on Multiple-Valued Logic
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions
ISMVL '99 Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic
Composition Trees in Finding Best Variable Orderings for ROBDDs
Proceedings of the conference on Design, automation and test in Europe
USING IF-THEN-ELSE DAGs FOR MULTI-LEVEL LOGIC MINIMIZATION
USING IF-THEN-ELSE DAGs FOR MULTI-LEVEL LOGIC MINIMIZATION
OBDD-based function decomposition: algorithms and implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disjoint-support Boolean decomposition combining functional and structural methods
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Decomposition of systems of Boolean functions determined by binary decision diagrams
Journal of Computer and Systems Sciences International
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.01 |
This paper presents a heuristic algorithm for disjoint decomposition of a Boolean function based on its ROBDD representation. Two distinct features make the algorithm feasible for large functions. First, for an n-variable function, it checks only O(n2) candidates for decomposition out of O(2n) possible ones. A special strategy for selecting candidates makes it likely that all other decompositions are encoded in the selected ones. Second, the decompositions for the approved candidates are computed using a novel IntervalCut algorithm. This algorithm does not require re-ordering of ROBDD. The combination of both techniques allows us to decompose the functions of size beyond that possible with the exact algorithms. The experimental results on 582 benchmark functions show that the presented heuristic finds 95% of all decompositions on average. For 526 of those functions, it finds 100% of the decompositions.