The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
Multi-level logic optimization
Logic Synthesis and Verification
Disjoint-support Boolean decomposition combining functional and structural methods
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A BDD-based fast heuristic algorithm for disjoint decomposition
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
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This article describes the use of if-then-else DAGs for multi-level logic minimization. A new canonical form for if-then-else DAGs, analogous to Bryant''s canonical form for binary decision diagrams (BDDs), is introduced. Two-cuts are defined for binary decision diagrams, and a relationship is exhibited between general if-then-else expressions and the two-cuts of a BDD for the same function. The canonical form is based on representing the lowest non-trivial two-cut in the corresponding BDD, instead of the highest two-cut, as in Bryant''s canonical form. The definitions of prime and irredundant expressions are extended to if-then-else DAGs. Expressions in Bryant''s canonical form or in the new canonical form can be shown to be prime and irredundant. Objective functions for minimization are discussed, and estimators for predicting the area and delay of the circuit produces after technology mapping are proposed. A brief discussion of methods for applying don''t-care information and for factoring expressions is included.