From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
Logic Synthesis for Manufacturability
IEEE Design & Test
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
A BDD-based fast heuristic algorithm for disjoint decomposition
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Near-optimal instruction selection on dags
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Statistical analysis of circuit timing using majorization
Communications of the ACM - A Blind Person's Interaction with Technology
Reconfigurable asynchronous logic automata: (RALA)
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated logic synthesis using simulated annealing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
An exact method to compute maximal implicants in a multivalued logic
ICOSSE'06 Proceedings of the 5th WSEAS international conference on System science and simulation in engineering
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Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.