Statistical analysis of circuit timing using majorization

Efficient algorithms for extracting the K most critical paths in timing analysis

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference

Gate sizing using a statistical delay model

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Logic Synthesis and Verification

Logic Synthesis and Verification

Statistical timing for parametric yield prediction of digital integrated circuits

Proceedings of the 40th annual Design Automation Conference

Timing Verification and the Timing Analysis program

DAC '82 Proceedings of the 19th Design Automation Conference

First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference

Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

High-performance CMOS variability in the 65-nm regime and beyond

IBM Journal of Research and Development - Advanced silicon technology

Design for Manufacturability and Statistical Design: A Comprehensive Approach

Design for Manufacturability and Statistical Design: A Comprehensive Approach

An accurate sparse matrix based framework for statistical static timing analysis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Statistical timing analysis using bounds and selective enumeration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems