Logic Synthesis for Manufacturability

Authors:
A. Nardi;A. L. Sangiovanni-Vincentelli
Affiliations:
California Univ., Berkeley, CA, USA;-
Venue:
IEEE Design & Test
Year:
2004

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Abstract

Typically, design optimization during synthesis is for area and/or performance, while optimization for yield occurs at the layout level. To obtain more effective yield improvement, this article proposes elevating the abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis.