Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Logic Synthesis for Manufacturability
IEEE Design & Test
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
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Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4 - 6%. This paper applies DFM to the routing. In particular, this paper analyzes the effects of various routing options on wafer productivity, and shows that if properly applied DFM can lead to a further die cost reduction of 9%.