An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
Shortest paths algorithms: theory and experimental evaluation
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
BddCut: Towards Scalable Symbolic Cut Enumeration
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA power reduction by guarded evaluation
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
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Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves "shortening" all paths found in the circuit at a cost of increasing the circuit area. In contrast, we present a synthesis approach which leverages slack budgeting to effectively minimize the critical path length without increasing the area of the design. Our results confirm that this is an effective method to control area while optimizing for delay. When compared to an area driven logic synthesis flow, we achieve a 32% reduction in logic depth and an 11% reduction in circuit delay when placed by VPR [1]; and when compared against a depth controlled logic synthesis flow without slack budgeting, we achieve an 8% reduction in logic depth and a 3% reduction in circuit delay when placed by VPR [1]. In both cases, the area penalty is negligible.