Introduction to algorithms
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A Polynomial Algorithm for Balancing Acyclic Data Flow Graphs
IEEE Transactions on Computers
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Balancing problems in acyclic networks
Discrete Applied Mathematics - Special volume: viewpoints on optimization
Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Component selection for high-performance pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Unification of budgeting and placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Delay budgeting for a timing-closure-driven design method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay budgeting in sequential circuit with application on FPGA placement
Proceedings of the 40th annual Design Automation Conference
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
Timing and Design Closure in Physical Design Flows
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Probabilistic Delay Budgeting for Soft Realtime Applications
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast timing closure by interconnect criticality driven delay relaxation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Incremental component implementation selection: enabling ECO in compositional system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Delay driven AIG restructuring using slack budget management
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Postplacement voltage assignment under performance constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and synthesis of programmable logic block with mixed LUT and macrogate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-space exploration of resource-sharing solutions for custom instruction set extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA placement by graph isomorphism (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This work presents a theoretical framework that optimally solves many open problems in time budgeting. Our approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation and min-skew time budget distribution. We show that many of the time management problems can be transformed into a min-cost flow instance that can be optimally and efficiently solved through well-known combinatorial techniques. Experiments include mapping of several designs, which are implemented using parameterized CoreGen IP cores, on Xilinx FPGA devices. Different time budgeting policies have been applied during the mapping stage. Our time management techniques always improved the area requirement of the implemented testbenches compared to a widely-used path-based method. We also compared the maximum budgeting and fairness in delay budget assignments. Our experimental results show that an average improvement of 19% in area can be achieved when fairness and maximum budgeting policies are combined, compared to pure maximum budgeting.