MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Delay budgeting in sequential circuit with application on FPGA placement
Proceedings of the 40th annual Design Automation Conference
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploration of pipelined FPGA interconnect structures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Architecture-level synthesis for automatic interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Due to decreasing transistor sizes and increasing clock frequency, interconnect delay is a dominant factor in achieving timing closure in deep sub-micron designs. Techniques like wire pipelining and retiming can manage delay of timing critical wires. The latency of the system, however, limits the total pipelining in the design. New techniques are, thus, needed at synthesis stage to consider the effect of critical wires in the design. In this work, we propose a novel intuitive algorithm, critical edge reduction (CER) algorithm, which produces a maximal delay budgeting solution under fixed latency while minimizing the number of critical wires. We also present an in-depth analysis of trade-off between maximum budgeting and critical edge minimization. We implemented our design flow using a set of MediaBench data paths on Xilinx VirtexE FPGA devices. Using our algorithm, the Xilinx Place and Route tool achieved timing closure, on average, 2.8 times faster than using maximum budgeting. The resulting average clock period using CER algorithm outperforms the one using maximum budgeting by 6%.