Exploration of pipelined FPGA interconnect structures

Authors:
Akshay Sharma;Katherine Compton;Carl Ebeling;Scott Hauck
Affiliations:
University of Washington, Seattle, WA;Northwestern University, Evanston, IL;University of Washington, Seattle, WA;University of Washington, Seattle, WA
Venue:
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Year:
2004

Citing 9
Cited 5

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect pipelining in a throughput-intensive FPGA architecture

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The case for registered routing switches in field programmable gate arrays

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
PipeRoute: a pipelining-aware router for FPGAs

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
RaPiD - Reconfigurable Pipelined Datapath

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Architecture Design of Reconfigurable Pipelined Datapaths

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Specifying and Compiling Applications for RaPiD

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast timing closure by interconnect criticality driven delay relaxation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

Microprocessors & Microsystems
Studying a GALS FPGA architecture using a parameterized automatic design flow

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A field programmable gate array media player for realmedia files

Journal of Computing Sciences in Colleges

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered IO terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD [4] architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.