Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Exploration of pipelined FPGA interconnect structures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Highly pipelined asynchronous FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Optimal partitioning of globally asychronous locally synchronous processor arrays
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low Power Two-Tier GALS Architecture for Multi Robot Collision Avoidance
Proceedings of Conference on Advances In Robotics
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Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. Globally Asynchronous Locally Synchronous (GALS) design is considered a potential solution to this issue. An important design decision in building a GALS FPGA architecture is to determine the appropriate GALS island size. A large GALS island will reduce the asynchronous communication overhead but the interconnect delay inside an island is increased. On the other hand, asynchronous communication overhead could be a major concern for a small GALS island size. In this paper, we propose a design flow to investigate this tradeoff. The input circuit is first divided into partitions according to the specified GALS island size and each partition is then implemented with commercially available CAD tools. The overall system performance is estimated by a performance evaluator. Experimental results validate our design flow and show a performance improvement of around 20% by adopting a GALS architecture.