IEEE Transactions on Computers
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum-Area Sequential Budgeting for FPGA
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Probabilistic Delay Budgeting for Soft Realtime Applications
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast timing closure by interconnect criticality driven delay relaxation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new algorithm, T-SBGT, which uses an LP formulation to solve the budgeting problem in sequential circuits and guarantees that the clock period constraints are met. We then utilize the skew-retiming equivalence relation [9] and retime the circuit. We demonstrate usefulness of our approach in the context of FPGA placement flow. An effective algorithm to minimize Flip-Flops (FFs) number after placement using the net slack is also proposed. The results show the placement flow improves timing by 9%, and reduces budget violations by 16% compared to the traditional flow. The post-placement FF reduction algorithm decreases the FF count by 19% on average.