Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Component selection for high-performance pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Unification of budgeting and placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Introduction to Algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Delay budgeting in sequential circuit with application on FPGA placement
Proceedings of the 40th annual Design Automation Conference
Global resource sharing for synthesis of control data flow graphs on FPGAs
Proceedings of the 40th annual Design Automation Conference
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. This paradigm shift calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior. We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multi-media applications on FPGAs show about 20% and 19% average energy and area improvement, respectively.