Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
A system for synthesizing optimized FPGA hardware from MATLAB
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Cameron: High Level Language Compilation for Reconfigurable Systems
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Combining module selection and resource sharing for efficient FPGA pipeline synthesis
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Resource sharing in pipelined CDFG synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Probabilistic Delay Budgeting for Soft Realtime Applications
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Graph-Based Procedural Abstraction
Proceedings of the International Symposium on Code Generation and Optimization
Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration
IEICE - Transactions on Information and Systems
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
Journal of Real-Time Image Processing
| Hi-index | 0.00 |
In this paper we discuss the global resource sharing problem during synthesis of control data flow graphs for FPGAs. We first define the Global Resource Sharing (GRS) problem. Then, we introduce the Global Inter Basic Block Resource Sharing (GIBBS) technique to solve the GRS problem. We developed five heuristics to solve the GRS problem. The first tries to minimize the number of connections between modules, the second considers the area gain, the third uses the criticality of operations assigned to resources as a measure for deciding on merging any given pair of resources, the fourth tries to capture common resource chains and overlap those to minimize both area and delay, and the fifth is the combination of these heuristics. While applying resource sharing, we also consider the execution frequency of the basic blocks. Using our techniques we synthesized several CDFGs representing applications from MediaBench suite. Our results show that, we can reduce the total area requirement by 44% on average (up to 59%) while increasing the execution time by 6% on average.