High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Java as a specification language for hardware-software systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware synthesis from C/C++ models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '99 Proceedings of the conference on Design, automation and test in Europe
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Using general-purpose programming languages for FPGA design
Proceedings of the 37th Annual Design Automation Conference
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Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Stream-Oriented FPGA Computing in the Streams-C High Level Language
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A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
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PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Fpga Hardware Synthesis From Matlab
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Optimized hardware synthesis for fpgas
Optimized hardware synthesis for fpgas
Parallelization of MATLAB Applications for a Multi-FPGA System
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Global resource sharing for synthesis of control data flow graphs on FPGAs
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Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
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Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
An overview of a compiler for mapping MATLAB programs onto FPGAs
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ACM Computing Surveys (CSUR)
Code transformations for embedded reconfigurable computing architectures
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Overview of a compiler for synthesizing MATLAB programs onto FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
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Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware.