Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB

  • Authors:
  • Malay Haldar;Anshuman Nayak;Alok Choudhary;Prith Banerjee

  • Affiliations:
  • MACH Design Systems, Inc., Schaumberg, IL;MACH Design Systems, Inc., Schaumberg, IL;MACH Design Systems, Inc., Schaumberg, IL;MACH Design Systems, Inc., Schaumberg, IL

  • Venue:
  • Proceedings of the 2001 Asia and South Pacific Design Automation Conference
  • Year:
  • 2001

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Abstract

We present a compiler that takes high level algorithms described in MATLAB and generates an optimized hardware for an FPGA with external memory. A framework is described to detect and exploit opportunities to pipeline loops in an optimal way. Effectiveness of the framework is demonstrated by synthesizing some image and signal processing applications. Starting from the MATLAB description of the applications, hardware is synthesized that runs on a Xilinx XC4028. The synthesized designs are equivalent to manually optimized designs in performance.