COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Hardware/software co-synthesis with memory hierarchies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
An approach to incremental design of distributed embedded systems
Proceedings of the 38th annual Design Automation Conference
A software development tool chain for a reconfigurable processor
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors
Proceedings of the 15th international symposium on System Synthesis
A system for synthesizing optimized FPGA hardware from MATLAB
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Continuous and high coverage self-testing of dynamically re-configurable systems
Parallel Computing - Parallel computing in image and video processing
The Garp Architecture and C Compiler
Computer
Efficient Pipelining of Nested Loops: Unroll-and-Squash
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Loop fusion and temporal common subexpression elimination in window-based loops
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A Generic Library for Adaptive Computing Environments
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Compiling Application-Specific Hardware
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Memory Access Schemes for Configurable Processors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Design of an adaptive architecture for energy efficient wireless image communication
Embedded processor design challenges
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the tenth international symposium on Hardware/software codesign
Journal of Systems Architecture: the EUROMICRO Journal
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Automatic compilation to a coarse-grained reconfigurable system-opn-chip
ACM Transactions on Embedded Computing Systems (TECS)
Using reconfigurability to achieve real-time profiling for hardware/software codesign
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Hardware/Software Design Space Exploration for a Reconfigurable Processor
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Bandwidth Management with a Reconfigurable Data Cache
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Parallel algorithms development for programmable logic devices
Advances in Engineering Software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems
Proceedings of the conference on Design, automation and test in Europe
Embedded real-time architecture for level-set-based active contours
EURASIP Journal on Applied Signal Processing
Efficient integration of pipelined IP blocks into automatically compiled datapaths
EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A novel SoC design methodology combining adaptive software and reconfigurable hardware
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hardware/software partitioning with multi-version implementation exploration
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Cache modeling in probabilistic execution time analysis
Proceedings of the 45th annual Design Automation Conference
Static analysis for fast and accurate design space exploration of caches
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Higher-level hardware synthesis of the KASUMI algorithm
Journal of Computer Science and Technology
Parallel algorithms development for programmable devices with application from cryptography
International Journal of Parallel Programming
Performance and power of cache-based reconfigurable computing
Proceedings of the 36th annual international symposium on Computer architecture
Intelligent Decoupled SAC-SVD Method in Color Space Transformation of Computer Vision
IEA/AIE '09 Proceedings of the 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: Next-Generation Applied Intelligence
A DVS-based pipelined reconfigurable instruction memory
Proceedings of the 46th Annual Design Automation Conference
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
A BBN-based framework for adaptive IP-reuse
Proceedings of the 6th FPGAworld Conference
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Support of Android lab modules for embedded system curriculum
WESE '10 Proceedings of the 2010 Workshop on Embedded Systems Education
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Hierarchical loop partitioning for rapid generation of runtime configurations
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
International Journal of Computer Applications in Technology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
The q2 profiling framework: driving application mapping for heterogeneous reconfigurable platforms
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Communication-aware HW/SW co-design for heterogeneous multicore platforms
Proceedings of the 2012 Workshop on Dynamic Analysis
Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A flexible general-purpose parallelizing architecture for nested loops in reconfigurable platforms
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
An analytical approach for fast and accurate design space exploration of instruction caches
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs fine-grained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU and datapath. The partitioning algorithm optimizes the global application execution time, including the software and hardware execution times, communication time and datapath reconfiguration time. Experimental results on real applications show that our algorithm is effective in rapidly finding close to optimal solutions.