Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Intellectual property re-use in embedded system co-design: an industrial case study
Proceedings of the 11th international symposium on System synthesis
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
PRISC Software Acceleration Techniques
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The increasing complexity of embedded systems and demands for quicker turn-around times require reuse of hardware and software components. Reconfigurable hardware technology opens a new implementation space where software and hardware design cycles might be very close in time and where a broader range of applications can be mapped on. The exploitation of reconfigurable platforms is often hampered by the lack of a unified software/(reconfigurable) hardware design flow. In this paper, we presented an enhancement of the POLIS framework for fast exploration and implementation of input-output subsystems on configurable systems-on-chip (CSoCs). The designer, given the functionality of the system described in POLIS, explores different solutions at the co-design level. Those solutions that, based on the estimation of performances, violate the timing requirements are pruned without the need of any FPGA synthesis and validation steps. The explored solutions satisfying the constraints are then implemented. The automatic generation of the hardware description and the hardware-software interface make the implementation step extremely fast leading to very short system design cycles.