Improving register allocation for subscripted variables
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The potential of data value speculation to boost ILP
ICS '98 Proceedings of the 12th international conference on Supercomputing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Limits of Instruction Level Parallelism with Data Value Speculation
VECPAR '98 Selected Papers and Invited Talks from the Third International Conference on Vector and Parallel Processing
Itanium 2 Processor Microarchitecture
IEEE Micro
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Automatic compilation of c for hybrid reconfigurable architectures
Automatic compilation of c for hybrid reconfigurable architectures
An Empirical Study of Data Speculation Use on the Intel Itanium 2 Processor
INTERACT '05 Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures
On the energy-efficiency of speculative hardware
Proceedings of the 2nd conference on Computing frontiers
Speculative Execution In High Performance Computer Architectures (Chapman & Hall/Crc Computer & Information Science Series)
IEEE Transactions on Computers
A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
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Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.