Data compression using static Huffman code-decode tables
Communications of the ACM
Data structure of Huffman codes and its application to efficient encoding and decoding
IEEE Transactions on Information Theory
The fast Fourier transform and its applications
The fast Fourier transform and its applications
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The benchmark book
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The C31 parallel benchmark suite - introduction and preliminary results
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
Minimizing FPGA Interconnect Delays
IEEE Design & Test
An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The LINPACK Benchmark: An Explanation
Proceedings of the 1st International Conference on Supercomputing
The RAW benchmark suite: computation structures for general purpose computing
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Video communications using rapidly reconfigurable hardware
IEEE Transactions on Circuits and Systems for Video Technology
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
A Generic Library for Adaptive Computing Environments
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
The Journal of Supercomputing
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper presents a benchmark suite for evaluating a configurable computing system's infrastructure, both tools and architecture. A novel aspect of this work is the use of stressmarks, benchmarks that focus on a specific characteristic or property of interest. This is in contrast to traditional approaches that utilize functional benchmarks, benchmarks that emphasize measuring end-to-end execution time. This suite can be used to assess a broad range of configurable computing systems, including single configurable devices, multiple configurable devices, and mixed architectures, such as fixed-plus-variable devices and hybrid systems. In addition, aspects that are particularly relevant to the domain of configurable computing, such as run-time reconfiguration and variable precision arithmetic, are considered. The paper provides an overview of the benchmark suite, presents some implementation results on an Annapolis Micro Systems WILDFORCE board, reflects on the benchmark suite developed, and briefly describes future work.