Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Runtime dependency analysis for loop pipelining in high-level synthesis
Proceedings of the 50th Annual Design Automation Conference
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We propose a universal method to automatically generate both data paths and the appropriate application-specific speculation-support logic from high-level C-language descriptions. Our approach aims to be lightweight by extending efficient statically-scheduled micro architectures with a limited dynamic token model to predict, commit, and replay speculation events. As a first source of speculative ness, we evaluate the use of data-value speculation to speed-up memory reads when targeting a reconfigurable adaptive computer.