The Omega test: a fast and practical integer programming algorithm for dependence analysis
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Speculative disambiguation: a compilation technique for dynamic memory disambiguation
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
International Journal of Parallel Programming - Special issue on parallel architectures and compilation techniques
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
Optimizing compilers for modern architectures: a dependence-based approach
Optimizing compilers for modern architectures: a dependence-based approach
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cost effective memory disambiguation for multimedia codes
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies
IEEE Transactions on Computers
Applying Data Speculation in Modulo Scheduled Loops
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Scalable Hardware Memory Disambiguation for High ILP Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Hybrid analysis: static & dynamic memory reference analysis
International Journal of Parallel Programming
Decomposing the load-store queue by function for power reduction and scalability
IBM Journal of Research and Development
Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Logical inference techniques for loop parallelization
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
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Research on High-Level Synthesis has mainly focused on applications with statically determinable characteristics and current tools often perform poorly in presence of data-dependent memory accesses. The reason is that they rely on conservative static scheduling strategies, which lead to inefficient implementations. In this work, we propose to address this issue by leveraging well-known techniques used in superscalar processors to perform runtime memory disambiguation. Our approach, implemented as a source-to-source transformation at the C level, demonstrates significant performance improvements for a moderate increase in area while retaining portability among HLS tools.