Task scheduling in parallel and distributed systems
Task scheduling in parallel and distributed systems
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
The nimber compiler for agile hardware: a research platform
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Adaptive Multiuser Online Reconfigurable Engine
IEEE Design & Test
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A C++ compiler for FPGA custom execution units synthesis
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A unified lower bound estimation technique for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new hardware algorithm for fast IP routing targeting programmable routers
Network control and engineering for Qos, security and mobility II
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The importance of efficient area and timing estimation is well established in high level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on functional units (FUs). Those models are not accurate enough to allow effective design space exploration since the effects of interconnects can indeed dominate the final design cost. The situation becomes even worst when the design is targeted to dynamically reconfigurable logic (DRL) technologies since the multiplexer delay may contribute heavily on the overall delay. In addition, large number of configurable logic blocks could be used for communication rather than for implementing FUs. In this paper we Present a new HLS design flow, which performs an accurate estimation on area and timing for DRL circuits. It takes into account not only FUs area and delay, but also the interconnection and communication effects. We select our DRL LSI circuit [M. Meribout, M. Motomura, Method for compiling high level programs into hardware, Japanese Patent: JSP2000-313818, 2000; M. Motomura et al., An embedded DRAM-FPGA chip with instantaneous logic reconfiguration, in: Symposium on VLSI Circuits, July 1997, pp. 55-56] as our main concentration. We tested our method with several benchmarks and the results show that we receive good performance of the design, with area and timing estimated efficiently.