Automatic compilation to a coarse-grained reconfigurable system-opn-chip

Authors:
Girish Venkataramani;Walid Najjar;Fadi Kurdahi;Nader Bagherzadeh;Wim Bohm;Jeff Hammes
Affiliations:
University of California, Riverside, CA;University of California, Riverside, CA;University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA;Colorado State University, Fort Collins, CO;Colorado State University, Fort Collins, CO
Venue:
ACM Transactions on Embedded Computing Systems (TECS)
Year:
2003

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Abstract

The rapid growth of device densities on silicon has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, one of the obstacles to the wider acceptance of this technology is its programmability. The application needs to be programmed in hardware description languages or an assembly equivalent, whereas most application programmers are used to the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. The Morphosys project proposes an SoC architecture consisting of reconfigurable hardware that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and automatically map the application onto the Morphosys architecture. The mapping process is static and it involves operation scheduling, processor allocation and binding, and register allocation in the context of the Morphosys architecture. The compiler also handles issues concerning data streaming and caching in order to minimize data transfer overhead. We have compiled some important image-processing kernels, and the generated schedules reflect an average speedup in execution times of up to 6× compared to the execution on 800 MHz Pentium III machines.