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In this paper, we describe the implementation of MorphoSys, areconfigurable processing system targeted at data-parallel andcomputation-intensive applications. The MorphoSys architectureconsists of a reconfigurable component (an array of reconfigurablecells) combined with a RISC control processor and a high bandwidthmemory interface. We briefly discuss the system-level model, arrayarchitecture, and control processor. Next, we present the detaileddesign implementation and the various aspects of physical layout ofdifferent sub-blocks of MorphoSys. The physical layout wasconstrained for 100 MHz operation, with low power consumption, andwas implemented using 0.35 μm, four metal layer CMOS (3.3 Volts)technology. We provide simulation results for the MorphoSysarchitecture (based on VHDL model) for some typical data-parallelapplications (video compression and automatic target recognition).The results indicate that the MorphoSys system can achievesignificantly better performance for most of these applications incomparison with other systems and processors.