Designing a coarse-grained reconfigurable architecture using loop self-pipelining

Authors:
Jinhui Xu;Guiming Wu;Yong Dou;Yazhuo Dong
Affiliations:
School of Computer Science, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;School of Computer Science, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;School of Computer Science, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;School of Computer Science, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

This paper introduces LEAP(Loop Engine on Array Processor), a novel coarse-grained reconfigurable architecture which accelerates applications through Loop Self-Pipelining (LSP) technique. The LSP can provide effective execution mode for application pipelining. By mapping and distributing the expression statements of high level programming languages onto processing elements array, the LEAP can step the loop iteration automatically. The LEAP architecture has no centralized control, no centralized multi-port registers and no centralized data memory. The LEAP has the ability to exploit loop-level, instruction-level, and task-level parallelism, and it is suitable choice for stream-based application domains, such as multimedia, DSP and graphics application.