Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Claude Elwood Shannon: collected papers
Claude Elwood Shannon: collected papers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Communications of the ACM
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Configware and morphware going mainstream
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Cyclic combinational circuits
IEEE Transactions on Computers
Exact combinational logic synthesis and non-standard circuit design
Proceedings of the 5th conference on Computing frontiers
The Art of Computer Programming, Volume 4, Fascicle 1: Bitwise Tricks & Techniques; Binary Decision Diagrams
A logic programming framework for combinational circuit synthesis
ICLP'07 Proceedings of the 23rd international conference on Logic programming
Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
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With the help of a simple reconfigurable logic gate that emulates conjunction, implication and a 1-bit memory cell, we devise a mechanism for synthesizing fine grained circuits that overlap multiple logic functions. The use of the gate as an integrated combinational and sequential logic building block enables processor architectures that naturally avoid the von Neumann bottleneck and support fine grained parallel execution. A symbolic model of the approach, including an exact synthesizer for small circuits, is provided as a literate Haskell program, available from http://logic.csci.unt.edu/tarau/research/2012/fsyn.hs.