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IEEE Transactions on Computers
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Claude Elwood Shannon: collected papers
Claude Elwood Shannon: collected papers
Bounding Fan-out in Logical Networks
Journal of the ACM (JACM)
Communications of the ACM
Logic Design of Digital Systems
Logic Design of Digital Systems
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
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The Art of Computer Programming, Volume 4, Fascicle 4: Generating All Trees--History of Combinatorial Generation (Art of Computer Programming)
Temperature-Adaptive Circuits on Reconfigurable Analog Arrays
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Evolutionary Design of Digital Circuits: Where Are Current Limits?
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach: First International Work-Conference on the Interplay Between Natural ... Part II (Lecture Notes in Computer Science)
Exact sat-based toffoli network synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Minimization of Logic Networks Under a Generalized Cost Function
IEEE Transactions on Computers
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Revisiting exact combinational circuit synthesis
Proceedings of the 2008 ACM symposium on Applied computing
A logic programming framework for combinational circuit synthesis
ICLP'07 Proceedings of the 23rd international conference on Logic programming
Synthesis of fredkin-toffoli reversible networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transistor-level circuit experiments using evolvable hardware
IWINAC'05 Proceedings of the First international work-conference on the Interplay Between Natural and Artificial Computation conference on Artificial Intelligence and Knowledge Engineering Applications: a bioinspired approach - Volume Part II
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
IEEE Transactions on Information Theory
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
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Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first based on how many gates are used to synthesize all binary operators, the second based on how many N-variable truth table values are covered by combining up to M gates from the library. By applying the indicators to an exhaustive enumeration of minimal universal libraries, two dual asymmetrical operations, Logic Implication "==" and Half XOR "