Reference manual of FORTRAN program ILLOD-(NOR-B) for optimal NOR networks
Reference manual of FORTRAN program ILLOD-(NOR-B) for optimal NOR networks
A study of current logic design problems: part i, design of diagnosable mos networks; part ii, minimum nor (nand) networks for parity functions of an arbitrary number of variables; part iii, minimum parallel binary adders with nor (nand) gates and their extensions to networks consisting of carry-save adders.
A study of nor/nand networks
Minimal parallel binary adders with and/or gates and a scheme for a compact parallel multiplier
Minimal parallel binary adders with and/or gates and a scheme for a compact parallel multiplier
Optimal One-Bit Full Adders With Different Types of Gates
IEEE Transactions on Computers
IEEE Transactions on Computers
Minimization of Logic Networks Under a Generalized Cost Function
IEEE Transactions on Computers
Minimum Parallel Binary Adders with NOR (NAND) Gates
IEEE Transactions on Computers
Parallel Binary Adders with a Minimum Number of Connections
IEEE Transactions on Computers
An Algorithm for NAND Decomposition Under Network Constraints
IEEE Transactions on Computers
Optimal Networks of NOR-OR Gates for Functions of Three Variables
IEEE Transactions on Computers
Design of Optimal Switching Networks by Integer Programming
IEEE Transactions on Computers
On a New Boolean Function with Applications
IEEE Transactions on Computers
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Exact combinational logic synthesis and non-standard circuit design
Proceedings of the 5th conference on Computing frontiers
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
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Design of logic networks, in single-rail input logic, with a minimum number of NOR gates for parity functions of an arbitrary number of variables is described. This is partly based on minimum networks for parity functions of a small number of variables which are designed by the integer programming logic design method. Although it is generally difficult to design minimum networks for functions of an arbitrarily large number of variables, we have previously designed minimum networks for adders of an arbitrary number of variables. The minimum networks for parity functions of an arbitrary number of variables discussed in this paper is another case. Many unique properties of minimum NOR networks for parity functions are shown. Minimum networks with NAND gates for parity functions can be easily obtained from those with NOR gates because of duality relationship between NAND and NOR.