An Approach to Multilevel Boolean Minimization
Journal of the ACM (JACM)
Journal of the ACM (JACM)
An Algorithm for Synthesis of Multiple-Output Combinational Logic
IEEE Transactions on Computers
Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"
IEEE Transactions on Computers
A computer program for the synthesis of combinational switching circuits
FOCS '61 Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961)
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Modular Replacement of Combinational Switching Networls
IEEE Transactions on Computers
Minimization of Logic Networks Under a Generalized Cost Function
IEEE Transactions on Computers
Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques
IEEE Transactions on Computers
The Synthesis of Minimal Hazardless TANT Networks
IEEE Transactions on Computers
Minimal TANT Networks of Functions with DON'T CARE'S and Some Complemented Input Variables
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
An Algorithm for Optimal NAND Cascade Logic Synthesis
IEEE Transactions on Computers
An Algorithm for Minimal TANT Network Generation
IEEE Transactions on Computers
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A branch-and-bound algorithm is presented for the synthesis of multioutput, multilevel, cycle-free NAND networks to realize an arbitrary given set of partially or completely specified combinational switching functions. In a programmed version of the algorithm, fan-in, fan-out, and level constraints may be specified. Cost may be specified as a nonnegative integer linear combination of gates and gate inputs. Further constraints and cost criteria are compatible with the algorithm. A first solution is constructed by a sequence of local decisions, and backtracking is executed to find improved solutions and to prove the optimality of the final solution.