An Approach to Multilevel Boolean Minimization

Absolute Bounds on Set Intersection and Union Sizes from Distribution Information

IEEE Transactions on Software Engineering

Optimization of combinational logic circuits based on compatible gates

DAC '93 Proceedings of the 30th international Design Automation Conference

Minimizing the routing cost during logic extraction

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Minimal Sets of Distinct Literals for a Logically Passive Function

Journal of the ACM (JACM)

Comment on Lawler's multilevel Boolean minimization

Communications of the ACM

The future of logic synthesis and verification

Logic Synthesis and Verification

XTRACT: Learning Document Type Descriptors from XML Document Collections

Data Mining and Knowledge Discovery

Reversible logic circuit synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

An application of multiple-valued logic to a design of programmable logic arrays

MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic

A new synthesis technique for multilevel combinational circuits

EURO-DAC '90 Proceedings of the conference on European design automation

An Algorithm for NAND Decomposition Under Network Constraints

IEEE Transactions on Computers