Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Exact combinational logic synthesis and non-standard circuit design
Proceedings of the 5th conference on Computing frontiers
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
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This correspondence presents the results of the synthesis of optimal feed-forward networks of just AND and OR gates for representative functions of the 222 n-p-n-equivalence classes into which all functions of four or fewer variables can be categorized. (Optimality here means minimization of the number of gates as the primary objective and minimization of the number of connections as the secondary objective, regardless of the number of levels. No fan-in or fan-out restriction is imposed.) Based on these results, instructions are given for obtaining optimal networks for desired functions of four or fewer variables which are not representative functions. The branch-and-bound computer program ILLOD-(AND-OR-B) was used to obtain the optimal networks presented.