Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Logic Networks of Carry-Save Adders
IEEE Transactions on Computers
Parallel Binary Adders with a Minimum Number of Connections
IEEE Transactions on Computers
A novel neural network parallel adder
IWANN'13 Proceedings of the 12th international conference on Artificial Neural Networks: advances in computational intelligence - Volume Part I
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Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this paper. The minimality of the number of NOR gates is proved for an arbitrary value of n. Also, it is proved that the adders must be a cascade of basic modules and that there exist many different types of basic modules. These adders have fewer gates and shorter net gate delays (or fewer connections) than the widely used carry-ripple adders which are a cascade of one-bit full adders. Design procedures of such adders are described, based on the integer-programming logic design method. There are many solutions but adders with few connections and those with few net gate delays (all these adders have the minimum number of gates) are shown as important examples. Altbough these adders are designed with NOR gates, the results in this paper are applicable to adders with NAND gates by duality conversion.