Revisiting exact combinational circuit synthesis
Proceedings of the 2008 ACM symposium on Applied computing
Exact combinational logic synthesis and non-standard circuit design
Proceedings of the 5th conference on Computing frontiers
Formal Reasoning About Causality Analysis
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
The analysis of cyclic circuits with Boolean satisfiability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
A logic programming framework for combinational circuit synthesis
ICLP'07 Proceedings of the 23rd international conference on Logic programming
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
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A collection of logic gates forms a combinational circuit if the outputs can be described as Boolean functions of the current input values only. Optimizing combinational circuitry, for instance, by reducing the number of gates (the area) or by reducing the length of the signal paths (the delay), is an overriding concern in the design of digital integrated circuits. The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. In fact, the idea that “combinational” and “acyclic” are synonymous terms is so thoroughly ingrained that many textbooks provide the latter as a definition of the former. And yet simple examples suggest that this is incorrect. In this dissertation, we advocate the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We demonstrate that circuits can be optimized effectively for area and for delay by introducing cycles. On the theoretical front, we discuss lower bounds and we show that certain cyclic circuits are one-half the size of the best possible equivalent a cyclic implementations. On the practical front, we describe an efficient approach for analyzing cyclic circuits, and we provide a general framework for synthesizing such circuits. On trials with industry-accepted benchmark circuits, we obtained significant improvements in area and delay in nearly all cases. Based on these results, we suggest that it is time to re-write the definition: combinational might well mean cyclic.