False loops through resource sharing
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Contemporary logic design
Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Digital Design: Principles and Practices
Digital Design: Principles and Practices
Making cyclic circuits acyclic
Proceedings of the 40th annual Design Automation Conference
The synthesis of cyclic combinational circuits
Proceedings of the 40th annual Design Automation Conference
Formal analysis of synchronous circuits
Formal analysis of synchronous circuits
Cyclic combinational circuits
The Necessity of Closed Circuit Loops in Minimal Combinational Circuits
IEEE Transactions on Computers
The Necessity of Feedback in Minimal Monotone Combinational Circuits
IEEE Transactions on Computers
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Reduction of interpolants for logic synthesis
Proceedings of the International Conference on Computer-Aided Design
Discrete Applied Mathematics
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. In previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We proposed a synthesis methodology and demonstrated that it produces significant improvements in area and in delay. The analysis method that we used to validate cyclic circuits was based on binary decision diagrams. In this paper, we propose a much more efficient technique for analysis based on Boolean satisfiability (SAT).