Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Test generation for cyclic combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
The Necessity of Feedback in Minimal Monotone Combinational Circuits
IEEE Transactions on Computers
On the Properties of Irredundant Logic Networks
IEEE Transactions on Computers
An Approach to Unified Methodology of Combinational Switching Circuits
IEEE Transactions on Computers
Formal Reasoning About Causality Analysis
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
The analysis of cyclic circuits with Boolean satisfiability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Discrete Applied Mathematics
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A cellular-logic approach is used to generate a family of multiple-output combinational switching circuits containing closed loops ( of the type that normally generate sequential behavior) and composed of simple gates. These networks contain fewer gates than any loop-free realizations. Some members of the family are oscillatory, while others are stable with multiple stable states, but the outputs remain quiescent in both cases. This result appears to have repercussions on some of the well-known optimality results of switching theory.