Digital logic testing and simulation
Digital logic testing and simulation
False loops through resource sharing
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
The Necessity of Closed Circuit Loops in Minimal Combinational Circuits
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
An Algebraic Model for the Analysis of Logical Circuits
IEEE Transactions on Computers
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Circuits that have an underlying acyclic topology are guaranteed to be combinational since feedback is necessary for sequential behavior. However, the reverse is not true, i.e., feedback is not a sufficient condition since there do exist combinational logic circuits that are cyclic. Such combinational circuits occur often in bus structures in data paths. This class of circuits has largely been ignored by conventional combinational single-stuck-at fault test pattern generators which assume that the circuit topology is acyclic. There has been no formal study of the test generation problem for these circuits and no algorithms and tools exist for this purpose. In practice, test generation for these circuits is handled in an awkward manner, typically with poor fault coverage. This paper provides, for the first time, a formal analysis of the test generation problem for these circuits. This analysis leads to a clear insight into generation of tests, as well as a classification of untestable faults for such circuits. We demonstrate that unlike acyclic circuits, where an untestable fault corresponds to a redundancy, cyclic combinational circuits may have untestable faults that do not correspond to redundancies. This insight is then translated to a testing algorithm which has been implemented in the program RAM. RAM has been successful is providing almost complete coverage on a range of typical examples, which Is significantly higher than that provided by conventional techniques.